Power Factor Corrected preregulator (PFC), using the L, and the lamp ballast stage with the L Referring to the application circuit (see fig.1), the AC mains voltage is rectified by a diodes bridge and delivered APPLICATION NOTE. The front-end stage of conventional off-line converters, typically made up of a full wave rectifier bridge with a capacitor filter, gets an unregulated DC bus from the. AN APPLICATION NOTE. May INTRODUCTION. Half bridge converter for electronic lamp ballast. Voltage fed series resonant half bridge inverters are.

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Analysis and design of Analysis and Design of Design of a flyback sw Thermal Design and Opt Among the various configurations that an Lbased flyback converter can assume, the high-PF one is particularly interesting because of both its peculiarity and the advantages it is able to offer.

AC-DC adapters for mobile or office equipment, off-line battery chargers and low-power SMPS are the most noticeable examples of application that this configuration can fit. This paper describes the equations governing such a kind of flyback converter with the aim of providing a number of relationships useful to the system designer. TM Flyback Configuration Three different configurations that an Lbased Vout flyback converter can assume have been identified.

Vac They are illustrated in fig. C Configurations a and b are basically conventional flyback converters. The former works in TM Transition Mode, i.

TL Configuration cwhich most exploits the aptitude of the L for performing power factor correction, works in TM too but quite differently: Apllication, the control loop has a narrow bandwidth so as to be little sensitive to the twice mains frequency ripple appearing at the output. Synchronised Flyback Configuration Figure 1c. In fact, despite a PF greater than 0. There are, however, several applications in the low-power range to which EMC norms do not apply that can applixation from the advantages offered by a high-PF flyback converter.

These advantages can be summarised as follows: This, in turn, minimises requirements on heatsinks; q low parts count, which helps reduce encumbrance applicatjon assembly cost. In addition, the unique features of the L offer remarkable advantages in numerous applications: An Applicattion high-PF flyback converter can easily meet Blue Angel regulations; q additional functions available: There are, on the other hand, some drawbacks, inherent in high-PF topologies, applcation the applications that such a converter can fit AC-DC adaptors, battery chargers, low-power SMPS, etc.

A large output capacitance will reduce its amount. Speeding up the control loop may lead to a compromise between a reasonably low output ripple and a PF still reasonably high; q poor transient response: Internal Block Diagram of the L F, depending on the output power is required: However, this is true also for a standard flyback; q the system is unable to cope with line missing cycles at heavy load unless an exceedingly high output capacitance is used.

In the following, the operation of a high-PF flyback converter will be discussed in nite and numerous relationships, useful for its design, will be established. For details concerning the operation of the L, please refer to Ref. Applictaion following assumptions will be made: As a result of the first two assumptions, the peak primary current is enveloped by a rectified sinusoid: Timing relationships The ON-time of the power switch is expressed notw The OFF-time is instead variable: To accomplish with this requirement, the primary inductance Lp will be properly selected not exceeding an upper limit.

Actually, to minimise the size of the transformer, the minimum frequency will usually be selected quite higher than 15 kHz, say kHz or more, so the value of Lp needs not have a tight tolerance. The duty cycle, that is the ratio between the ON-time and the switching period, will vary with the instantaneous line voltage as well because of the variation of TOFFas it is possible to find by dividing eqn. In the real-world operation, it must ll6561 considered that TON cannot go below a minimum amount and so will do the switching period as well.

This minimum typically, 0. When this minimum is reached, the energy drawn each cycle exceeds the short-term demand from the load, applicatioon the control loop 6l561 some cycles to be skipped so as to maintain the long-term energy balance. When not load is so low that many cycles need to be skipped, the amplitude of the drain voltage ringing becomes so small that it can no longer trigger the ZCD Block of the L In that case the internal starter of the IC will start a new switching cycles sequence.

Something similar applies to the duty cycle as well, which eqn. The effect of that on the overall operation is however negligible because the energy processed near a zero-crossing is very little.

The following relationships relate IPKp to the input power P in and allow both to explicate the timing relationships and to calculate all the currents circulating in the circuit.

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As earlier stated by equation 1during each half-cycle the height of these triangles varies with the instantaneousline voltage: Primary Current fL time scale 1 0. Since Kv cannot be zero which would require the reflected voltage to tend to infinityflyback topology does not permit unity power factor even in the ideal case, unlike boost topology. High-PF Flyback characteristic functions: F2 x diagram 0. F2 Kv which will assume its maximum value at minimum mains voltage.

The total RMS value of the primary current, useful for power loss estimate on the primary side, is calculated considering the RMS value of each triangle of Ip t and averaging over a line half-cycle: F1 x diagram 0.

Its twice line frequency representation will be again the average over a switching cycle: According to assumption 3IPKs would equal n? To consider a more realistic case the secondary peak current is slightly less than n?

By equalling the average value of 11 over one line half-cycle to Iout, it is possible to find: F3 x diagram 0. IRMS1 can be simply calculated from the numerator of In fact 9 contains also the energy contribution due to the switching frequency, while equation 13 – and therefore IRMSin too – refers only to line frequency quantities. Inserting 14 and 15 in 13 yields the theoretical expression of PF note that it depends only on Kv. Its diagram, depicted in fig.

For practical use, PF can be approximated by: K2 v 16 Figure 8. Still under the assumption of an ideally sinusoidal input voltage, the THD is related to the Power Factor by the following relationship: For a given reflected voltage, it shows how the Total Harmonic Distortion degrades when the line voltage builds up.

Transformer The design of the transformer is a complex procedure that involves several steps: Moreover, additional considerations concerning the assembly are needed for meeting safety requirements, maximising magnetic coupling and minimising parasitic high frequency effects, not to mention the constraints imposed by the specific application, if any. Some parameters are needed to start the design of the transformer.

## An966 Application Note L6561, Enhanced Transition Mode Power Factor Corrector

The maximum primary inductance will be calculated by solving 5 for Lp: Pinmax or by simply looking up the diagram of fig. The value taken from fig. The primary-to-secondary turns ratio will be given by: Anyway, as a design aid to core selection, two expressions for determining the minimum required core Area-Product winding window area times effective magnetic cross section will be provided: Kv Formula 17 assumes that the maximum peak flux density inside the core is limited by core saturation and that all transformer losses are located in the windings; 18 assumes that core losses limit the flux swing and the total dissipation are half due to core losses and half to windings losses.

Common to both formulae are the following Figure Minimum Transformer AP required for a assumptions: Core losses become dominant for core selection above 45 kHz at this power level. Clamp network The overvoltage spikes due to the leakage inductance of the transformer are usually limited by an RCD clamp network, as illustrated in fig. It can be advantageous the use of a zener or transil clamp see fig.

Considering the RCD clamp, the capacitor is selected so as to have an assigned overvoltage? V as a rule of thumb, half the reflected voltage at turn-off such that the voltage rating of the MOSFET is never exceeded. From energetic balance, it is possible to write: F2 Kvmin The capacitor undergoes large current spikes and therefore it should be a very low ESR type with polypropylene or polystyrene film dielectric. The power rating of this resistor can be estimated by considering the DC dissipation due to the reflected voltage and the leakage inductance energy: R 2 The blocking diode will be not only a very fast recovery type but will also feature a very fast turn-on time.

In fact, the instantaneous forward drop at turn-on generates a spike, exceeding the overvoltage? V, that must be small. Considering a zener or a transil, its clamping voltage can be approximated with its breakdown voltage. In fact, the peak current is quite small and it is possible to neglect the contribution due to the dynamic resistance.

The breakdown voltage, which should account for the drift due to the temperature rise, will then be: The steady-state power dissipation capability must be at least: VR while there is no concern about its peak power dissipation, since this is defined for power pulses of 1 ms leakage inductance is typically demagnetized in less than 1? As to the blocking diode, what said earlier about the one of the RCD clamp still applies.

Output Capacitor The output capacitor undergoes the AC component of the secondary current Is tsee fig 3. Besides, to achieve a reasonably high PF, the voltage control loop is slow typically, its bandwidth is below Hz. As a result, there is a quite large voltage ripple appearing across the output capacitor. This ripple has two components.

One is related to the high frequency triangles and depends almost entirely on wpplication ESR of the output capacitor, being the capacitive contribution practically negligible.

Its maximum amplitude, occurring on the peak of the sinusoid, will be: ESR The second component of the ripple is related to the twice line frequency envelope and, unlike the high frequency component, depends on applicqtion capacitance value, while the ESR contribution can be neglected.