For a description of the parity error scheme and parity error signals, refer to the Cortex*-A9 Technical Reference Manual, available on the ARM* website. ARM CORTEX A9 MPCORE TECHNICAL REFERENCE MANUAL ULENHBXHSZ ULENHBXHSZ | PDF | 95 Pages | ARM CORTEX A9. f For further information about Cortex-A9 MPCore configurable options, refer to the. Introduction chapter of the Cortex-A9 MPCore Technical Reference Manual, .
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Release Information The following changes have been made to this book. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements.
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This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Confidentiality Status This document is. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of mznual agreement entered into by ARM and the party that ARM delivered this document to.
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Product Status The information in this document is final, that is for a developed product. It contains the following sections: About this book on page vi Feedback on page x. Cirtex-a9 revision status The rnpn identifier indicates the revision status of the product described in this book, where: Intended audience This book referejce written for hardware and software engineers implementing Cortex-A9 system designs.
It provides information that enables designers to integrate the processor into a target system. Using this book This book is organized into the following chapters: There are implementation-specific differences.
Chapter 4 Global timer, private timers, and watchdog registers Read this for a description of the Cortex-A9 MPCore timer and watchdog registers. Chapter 5 Clocks, Resets, and Power Management Read this for a description of the clocking modes and the reset signals.
Techhnical chapter also describes the power management facilities.
Typographical conventions Timing diagrams Signals on page viii. Typographical conventions The typographical conventions are: Highlights interface elements, such as menu names.
Also used for terms in descriptive lists, where appropriate. Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. Denotes arguments to monospace text where the argument is to be replaced by a specific value.
Denotes language keywords when used outside example code. Timing diagrams The figure named Key to timing diagram conventions on page viii explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that technicao not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.
Main Processor – Vita Development Wiki
Signal level Lower-case n The level of an asserted signal depends on whether the signal is active-high or active-low. At the start or end of crotex-a9 signal name denotes an active-low signal. Additional reading This section lists publications referencf ARM and by third parties. See Infocenter, for access to ARM documentation. ARM publications This book contains information that is specific to techhnical product. See the following documents for other relevant information: Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: The product revision or version.
An explanation with as much information as you can provide. Include symptoms and diagnostic procedures if appropriate. Feedback on content If you have comments on content then send an to Give: ARM also welcomes general suggestions for additions and improvements.
A set of private memory-mapped peripherals, including a global timer, and a watchdog and private timer for each Cortex-A9 processor present in the cluster. An integrated Interrupt Controller that is an implementation of the Generic Interrupt Controller architecture. ARM recommends you implement uniform configurations for software ease of use. The major options are: See Configurable options on page Figure on page shows an example multiprocessor configuration. In this configuration, an SCU is still provided.
The Fechnical, and an additional master port, are still available as configuration options. It does not duplicate information from these sources ARM architecture The Cortex-A9 processor implements the ARMv7-A architecture profile that includes the following architecture extensions: Includes support for floating-point operations. If this option is implemented then reterence FPU option cannot also be implemented. See Parity error eeference on page A for a description of the signals.
Memory regions used for these registers must be marked as Mcpore or Strongly-ordered in the translation tables. Access to the private memory region is little-endian only. The Cortex-A9 MPCore processor also provides a separate interrupt interface, with a configurable number of interrupts lines, up toconnected to its internal Interrupt Controller.
With the exception of a few debug configuration signals, the debug interfaces of the individual Cortex-A9 processors are presented externally so that each processor can be debugged independently. To be kept coherent, the memory must be marked as Write-Back, Shareable, Normal memory. Note When tevhnical Shareable attribute is applied to manuzl memory region that is not Write-Back Normal memory, data held in this region is treated as Noncacheable Registers with multiprocessor uses The following registers, described in the Nanual TRM, have multiprocessor uses.
See Additional reading on page viii for more information about the books described in this section. For information on the relevant architectural standards and protocols, see Compliance on page Documentation Design flow The Cortex-A9 MPCore documentation is as follows: It is required at all stages of the design flow. The choices made in the design flow can mean that some behavior described in the TRM is not relevant.
Before it can be used in a product, it must go through the following processes: Implementation The implementer configures mpcorw synthesizes the RTL to produce a hard macrocell. This might include integrating RAMs into the design.
Integration The integrator connects the implemented design into a SoC.
This includes connecting it to a memory system and peripherals. Programming This is the last process. The system programmer develops the software required to configure and initialize the Cortex-A9 MPCore processor, and tests the required application cortex-w9. For MCUs, often a single design team integrates the processor before synthesizing the complete design.
Alternatively, the team can synthesise the processor on its own or partially integrated, to produce a macrocell that is then integrated, possibly by a separate team.
Build configuration The implementer chooses the options that affect how the RTL source files are pre-processed. These options usually include or exclude logic that affects one or more of the area, maximum frequency, and features of the resulting macrocell. Configuration inputs The integrator configures some features of the Cortex-A9 MPCore processor by tying inputs to specific values.
These configurations affect the start-up behavior before any software configuration is made. They can also limit the options available to the software. Software configuration The programmer configures the Cortex-A9 MPCore processor by programming particular values into registers. Note This manual refers to implementation-defined features that are applicable to build configuration options.
Reference to a feature that is included means that the appropriate build and pin configuration options are selected. Reference to an enabled feature means one that has also been configured by software. The differences between the two revisions are: Neither of these changes affect the functionality described in this document.
In r1p0 there is a global timer. See About the Global Timer on page Conditions for coherent snoop for ACP requests amended. See Table on page See Clocks on page Change to the behavior of the comparators for each processor with the global timer. The SCU functions are to: All SCU registers are byte accessible and are reset by nscureset.
This register is writable if the relevant bits in the SAC are set. Usage constraints This register is writable in Secure state if the relevant bit in the SAC register is set. Configurations Available in all Cortex-A9 multiprocessor configurations.